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/* USER CODE BEGIN Header */ |
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/**
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****************************************************************************** |
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* @file : main.h |
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* @brief : Header for main.c file. |
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* This file contains the common defines of the application. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __MAIN_H |
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#define __MAIN_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f7xx_hal.h" |
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/* Private includes ----------------------------------------------------------*/ |
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/* USER CODE BEGIN Includes */ |
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/* USER CODE END Includes */ |
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/* Exported types ------------------------------------------------------------*/ |
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/* USER CODE BEGIN ET */ |
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/* USER CODE END ET */ |
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/* Exported constants --------------------------------------------------------*/ |
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/* USER CODE BEGIN EC */ |
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/* USER CODE END EC */ |
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/* Exported macro ------------------------------------------------------------*/ |
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/* USER CODE BEGIN EM */ |
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/* USER CODE END EM */ |
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void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); |
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/* Exported functions prototypes ---------------------------------------------*/ |
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void Error_Handler(void); |
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/* USER CODE BEGIN EFP */ |
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/* USER CODE END EFP */ |
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/* Private defines -----------------------------------------------------------*/ |
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __MAIN_H */ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/**
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****************************************************************************** |
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* @file stm32f7xx_hal_conf_template.h |
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* @author MCD Application Team |
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* @brief HAL configuration template file. |
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* This file should be copied to the application folder and renamed |
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* to stm32f7xx_hal_conf.h. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved.</center></h2> |
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* |
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* This software component is licensed by ST under BSD 3-Clause license, |
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* the "License"; You may not use this file except in compliance with the |
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* License. You may obtain a copy of the License at: |
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* opensource.org/licenses/BSD-3-Clause |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F7xx_HAL_CONF_H |
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#define __STM32F7xx_HAL_CONF_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Exported types ------------------------------------------------------------*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/* ########################## Module Selection ############################## */ |
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/**
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* @brief This is the list of modules to be used in the HAL driver |
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*/ |
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#define HAL_MODULE_ENABLED |
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/* #define HAL_ADC_MODULE_ENABLED */ |
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/* #define HAL_CRYP_MODULE_ENABLED */ |
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/* #define HAL_CAN_MODULE_ENABLED */ |
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/* #define HAL_CEC_MODULE_ENABLED */ |
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/* #define HAL_CRC_MODULE_ENABLED */ |
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/* #define HAL_CRYP_MODULE_ENABLED */ |
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/* #define HAL_DAC_MODULE_ENABLED */ |
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/* #define HAL_DCMI_MODULE_ENABLED */ |
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/* #define HAL_DMA2D_MODULE_ENABLED */ |
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/* #define HAL_ETH_MODULE_ENABLED */ |
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/* #define HAL_NAND_MODULE_ENABLED */ |
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/* #define HAL_NOR_MODULE_ENABLED */ |
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/* #define HAL_SRAM_MODULE_ENABLED */ |
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/* #define HAL_SDRAM_MODULE_ENABLED */ |
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/* #define HAL_HASH_MODULE_ENABLED */ |
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/* #define HAL_I2S_MODULE_ENABLED */ |
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/* #define HAL_IWDG_MODULE_ENABLED */ |
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/* #define HAL_LPTIM_MODULE_ENABLED */ |
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#define HAL_LTDC_MODULE_ENABLED |
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#define HAL_QSPI_MODULE_ENABLED |
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/* #define HAL_RNG_MODULE_ENABLED */ |
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#define HAL_RTC_MODULE_ENABLED |
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/* #define HAL_SAI_MODULE_ENABLED */ |
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#define HAL_SD_MODULE_ENABLED |
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/* #define HAL_MMC_MODULE_ENABLED */ |
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/* #define HAL_SPDIFRX_MODULE_ENABLED */ |
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#define HAL_SPI_MODULE_ENABLED |
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#define HAL_TIM_MODULE_ENABLED |
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#define HAL_UART_MODULE_ENABLED |
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/* #define HAL_USART_MODULE_ENABLED */ |
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/* #define HAL_IRDA_MODULE_ENABLED */ |
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/* #define HAL_SMARTCARD_MODULE_ENABLED */ |
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/* #define HAL_WWDG_MODULE_ENABLED */ |
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/* #define HAL_PCD_MODULE_ENABLED */ |
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/* #define HAL_HCD_MODULE_ENABLED */ |
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/* #define HAL_DFSDM_MODULE_ENABLED */ |
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/* #define HAL_DSI_MODULE_ENABLED */ |
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/* #define HAL_JPEG_MODULE_ENABLED */ |
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/* #define HAL_MDIOS_MODULE_ENABLED */ |
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#define HAL_SMBUS_MODULE_ENABLED |
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/* #define HAL_EXTI_MODULE_ENABLED */ |
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#define HAL_GPIO_MODULE_ENABLED |
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#define HAL_EXTI_MODULE_ENABLED |
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#define HAL_DMA_MODULE_ENABLED |
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#define HAL_RCC_MODULE_ENABLED |
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#define HAL_FLASH_MODULE_ENABLED |
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#define HAL_PWR_MODULE_ENABLED |
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#define HAL_I2C_MODULE_ENABLED |
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#define HAL_CORTEX_MODULE_ENABLED |
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/* ########################## HSE/HSI Values adaptation ##################### */ |
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. |
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* This value is used by the RCC HAL module to compute the system frequency |
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* (when HSE is used as system clock source, directly or through the PLL). |
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*/ |
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#if !defined (HSE_VALUE) |
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#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ |
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#endif /* HSE_VALUE */ |
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#if !defined (HSE_STARTUP_TIMEOUT) |
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#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ |
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#endif /* HSE_STARTUP_TIMEOUT */ |
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/**
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* @brief Internal High Speed oscillator (HSI) value. |
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* This value is used by the RCC HAL module to compute the system frequency |
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* (when HSI is used as system clock source, directly or through the PLL). |
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*/ |
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#if !defined (HSI_VALUE) |
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#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
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#endif /* HSI_VALUE */ |
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/**
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* @brief Internal Low Speed oscillator (LSI) value. |
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*/ |
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#if !defined (LSI_VALUE) |
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#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ |
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
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The real value may vary depending on the variations |
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in voltage and temperature. */ |
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/**
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* @brief External Low Speed oscillator (LSE) value. |
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*/ |
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#if !defined (LSE_VALUE) |
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#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ |
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#endif /* LSE_VALUE */ |
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#if !defined (LSE_STARTUP_TIMEOUT) |
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#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ |
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#endif /* LSE_STARTUP_TIMEOUT */ |
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/**
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* @brief External clock source for I2S peripheral |
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* This value is used by the I2S HAL module to compute the I2S clock source |
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* frequency, this source is inserted directly through I2S_CKIN pad. |
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*/ |
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#if !defined (EXTERNAL_CLOCK_VALUE) |
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#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ |
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#endif /* EXTERNAL_CLOCK_VALUE */ |
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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=== you can define the HSE value in your toolchain compiler preprocessor. */ |
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/* ########################### System Configuration ######################### */ |
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/**
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* @brief This is the HAL system configuration section |
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*/ |
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#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ |
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#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ |
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#define USE_RTOS 0U |
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#define PREFETCH_ENABLE 0U |
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#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ |
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#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ |
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#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ |
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#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ |
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#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ |
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#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ |
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#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ |
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#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ |
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#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ |
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#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ |
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#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ |
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#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ |
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#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ |
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#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ |
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#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ |
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#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ |
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#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ |
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#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ |
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#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ |
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#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ |
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#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ |
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#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ |
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#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ |
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#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ |
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#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ |
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#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ |
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#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ |
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#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ |
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#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ |
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#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ |
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#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ |
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#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ |
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#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ |
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#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ |
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#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ |
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#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ |
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#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ |
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#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ |
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#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ |
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/* ########################## Assert Selection ############################## */ |
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/**
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* @brief Uncomment the line below to expanse the "assert_param" macro in the |
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* HAL drivers code |
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*/ |
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/* #define USE_FULL_ASSERT 1U */ |
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/* ################## Ethernet peripheral configuration ##################### */ |
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/* Section 1 : Ethernet peripheral configuration */ |
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ |
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#define MAC_ADDR0 2U |
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#define MAC_ADDR1 0U |
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#define MAC_ADDR2 0U |
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#define MAC_ADDR3 0U |
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#define MAC_ADDR4 0U |
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#define MAC_ADDR5 0U |
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/* Definition of the Ethernet driver buffers size and count */ |
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ |
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ |
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#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
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#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
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/* Section 2: PHY configuration section */ |
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/* DP83848_PHY_ADDRESS Address*/ |
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#define DP83848_PHY_ADDRESS 0x01U |
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
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#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) |
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/* PHY Configuration delay */ |
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) |
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#define PHY_READ_TO ((uint32_t)0x0000FFFFU) |
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#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) |
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/* Section 3: Common PHY Registers */ |
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#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ |
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#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ |
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#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ |
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#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ |
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ |
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ |
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ |
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ |
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ |
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ |
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#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ |
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#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ |
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ |
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#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ |
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ |
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/* Section 4: Extended PHY Registers */ |
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#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ |
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#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ |
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ |
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/* ################## SPI peripheral configuration ########################## */ |
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/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
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* Activated: CRC code is present inside driver |
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* Deactivated: CRC code cleaned from driver |
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*/ |
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#define USE_SPI_CRC 0U |
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/* Includes ------------------------------------------------------------------*/ |
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/**
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* @brief Include module's header file |
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*/ |
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#ifdef HAL_RCC_MODULE_ENABLED |
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#include "stm32f7xx_hal_rcc.h" |
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#endif /* HAL_RCC_MODULE_ENABLED */ |
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#ifdef HAL_EXTI_MODULE_ENABLED |
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#include "stm32f7xx_hal_exti.h" |
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#endif /* HAL_EXTI_MODULE_ENABLED */ |
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#ifdef HAL_GPIO_MODULE_ENABLED |
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#include "stm32f7xx_hal_gpio.h" |
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#endif /* HAL_GPIO_MODULE_ENABLED */ |
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#ifdef HAL_DMA_MODULE_ENABLED |
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#include "stm32f7xx_hal_dma.h" |
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#endif /* HAL_DMA_MODULE_ENABLED */ |
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#ifdef HAL_CORTEX_MODULE_ENABLED |
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#include "stm32f7xx_hal_cortex.h" |
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#endif /* HAL_CORTEX_MODULE_ENABLED */ |
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#ifdef HAL_ADC_MODULE_ENABLED |
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#include "stm32f7xx_hal_adc.h" |
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#endif /* HAL_ADC_MODULE_ENABLED */ |
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#ifdef HAL_CAN_MODULE_ENABLED |
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#include "stm32f7xx_hal_can.h" |
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#endif /* HAL_CAN_MODULE_ENABLED */ |
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#ifdef HAL_CEC_MODULE_ENABLED |
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#include "stm32f7xx_hal_cec.h" |
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#endif /* HAL_CEC_MODULE_ENABLED */ |
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#ifdef HAL_CRC_MODULE_ENABLED |
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#include "stm32f7xx_hal_crc.h" |
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#endif /* HAL_CRC_MODULE_ENABLED */ |
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#ifdef HAL_CRYP_MODULE_ENABLED |
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#include "stm32f7xx_hal_cryp.h" |
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#endif /* HAL_CRYP_MODULE_ENABLED */ |
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#ifdef HAL_DMA2D_MODULE_ENABLED |
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#include "stm32f7xx_hal_dma2d.h" |
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#endif /* HAL_DMA2D_MODULE_ENABLED */ |
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#ifdef HAL_DAC_MODULE_ENABLED |
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#include "stm32f7xx_hal_dac.h" |
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#endif /* HAL_DAC_MODULE_ENABLED */ |
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#ifdef HAL_DCMI_MODULE_ENABLED |
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#include "stm32f7xx_hal_dcmi.h" |
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#endif /* HAL_DCMI_MODULE_ENABLED */ |
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#ifdef HAL_ETH_MODULE_ENABLED |
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#include "stm32f7xx_hal_eth.h" |
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#endif /* HAL_ETH_MODULE_ENABLED */ |
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#ifdef HAL_FLASH_MODULE_ENABLED |
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#include "stm32f7xx_hal_flash.h" |
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#endif /* HAL_FLASH_MODULE_ENABLED */ |
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#ifdef HAL_SRAM_MODULE_ENABLED |
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#include "stm32f7xx_hal_sram.h" |
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#endif /* HAL_SRAM_MODULE_ENABLED */ |
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#ifdef HAL_NOR_MODULE_ENABLED |
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#include "stm32f7xx_hal_nor.h" |
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#endif /* HAL_NOR_MODULE_ENABLED */ |
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#ifdef HAL_NAND_MODULE_ENABLED |
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#include "stm32f7xx_hal_nand.h" |
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#endif /* HAL_NAND_MODULE_ENABLED */ |
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#ifdef HAL_SDRAM_MODULE_ENABLED |
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#include "stm32f7xx_hal_sdram.h" |
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#endif /* HAL_SDRAM_MODULE_ENABLED */ |
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#ifdef HAL_HASH_MODULE_ENABLED |
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#include "stm32f7xx_hal_hash.h" |
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#endif /* HAL_HASH_MODULE_ENABLED */ |
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#ifdef HAL_I2C_MODULE_ENABLED |
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#include "stm32f7xx_hal_i2c.h" |
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#endif /* HAL_I2C_MODULE_ENABLED */ |
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#ifdef HAL_I2S_MODULE_ENABLED |
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#include "stm32f7xx_hal_i2s.h" |
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#endif /* HAL_I2S_MODULE_ENABLED */ |
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#ifdef HAL_IWDG_MODULE_ENABLED |
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#include "stm32f7xx_hal_iwdg.h" |
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#endif /* HAL_IWDG_MODULE_ENABLED */ |
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#ifdef HAL_LPTIM_MODULE_ENABLED |
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#include "stm32f7xx_hal_lptim.h" |
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#endif /* HAL_LPTIM_MODULE_ENABLED */ |
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#ifdef HAL_LTDC_MODULE_ENABLED |
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#include "stm32f7xx_hal_ltdc.h" |
|||
#endif /* HAL_LTDC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_PWR_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_pwr.h" |
|||
#endif /* HAL_PWR_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_QSPI_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_qspi.h" |
|||
#endif /* HAL_QSPI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_RNG_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_rng.h" |
|||
#endif /* HAL_RNG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_RTC_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_rtc.h" |
|||
#endif /* HAL_RTC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SAI_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_sai.h" |
|||
#endif /* HAL_SAI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SD_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_sd.h" |
|||
#endif /* HAL_SD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_MMC_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_mmc.h" |
|||
#endif /* HAL_MMC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SPDIFRX_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_spdifrx.h" |
|||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SPI_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_spi.h" |
|||
#endif /* HAL_SPI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_TIM_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_tim.h" |
|||
#endif /* HAL_TIM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_UART_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_uart.h" |
|||
#endif /* HAL_UART_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_USART_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_usart.h" |
|||
#endif /* HAL_USART_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_IRDA_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_irda.h" |
|||
#endif /* HAL_IRDA_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SMARTCARD_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_smartcard.h" |
|||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_WWDG_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_wwdg.h" |
|||
#endif /* HAL_WWDG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_PCD_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_pcd.h" |
|||
#endif /* HAL_PCD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_HCD_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_hcd.h" |
|||
#endif /* HAL_HCD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DFSDM_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_dfsdm.h" |
|||
#endif /* HAL_DFSDM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DSI_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_dsi.h" |
|||
#endif /* HAL_DSI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_JPEG_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_jpeg.h" |
|||
#endif /* HAL_JPEG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_MDIOS_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_mdios.h" |
|||
#endif /* HAL_MDIOS_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SMBUS_MODULE_ENABLED |
|||
#include "stm32f7xx_hal_smbus.h" |
|||
#endif /* HAL_SMBUS_MODULE_ENABLED */ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
#ifdef USE_FULL_ASSERT |
|||
/**
|
|||
* @brief The assert_param macro is used for function's parameters check. |
|||
* @param expr: If expr is false, it calls assert_failed function |
|||
* which reports the name of the source file and the source |
|||
* line number of the call that failed. |
|||
* If expr is true, it returns no value. |
|||
* @retval None |
|||
*/ |
|||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
|||
/* Exported functions ------------------------------------------------------- */ |
|||
void assert_failed(uint8_t* file, uint32_t line); |
|||
#else |
|||
#define assert_param(expr) ((void)0U) |
|||
#endif /* USE_FULL_ASSERT */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F7xx_HAL_CONF_H */ |
|||
|
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
@ -0,0 +1,69 @@ |
|||
/* USER CODE BEGIN Header */ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f7xx_it.h |
|||
* @brief This file contains the headers of the interrupt handlers. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
|||
* All rights reserved.</center></h2> |
|||
* |
|||
* This software component is licensed by ST under BSD 3-Clause license, |
|||
* the "License"; You may not use this file except in compliance with the |
|||
* License. You may obtain a copy of the License at: |
|||
* opensource.org/licenses/BSD-3-Clause |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
/* USER CODE END Header */ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F7xx_IT_H |
|||
#define __STM32F7xx_IT_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Private includes ----------------------------------------------------------*/ |
|||
/* USER CODE BEGIN Includes */ |
|||
|
|||
/* USER CODE END Includes */ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* USER CODE BEGIN ET */ |
|||
|
|||
/* USER CODE END ET */ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* USER CODE BEGIN EC */ |
|||
|
|||
/* USER CODE END EC */ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/* USER CODE BEGIN EM */ |
|||
|
|||
/* USER CODE END EM */ |
|||
|
|||
/* Exported functions prototypes ---------------------------------------------*/ |
|||
void NMI_Handler(void); |
|||
void HardFault_Handler(void); |
|||
void MemManage_Handler(void); |
|||
void BusFault_Handler(void); |
|||
void UsageFault_Handler(void); |
|||
void SVC_Handler(void); |
|||
void DebugMon_Handler(void); |
|||
void PendSV_Handler(void); |
|||
void SysTick_Handler(void); |
|||
/* USER CODE BEGIN EFP */ |
|||
|
|||
/* USER CODE END EFP */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F7xx_IT_H */ |
|||
|
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,203 @@ |
|||
/* USER CODE BEGIN Header */ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f7xx_it.c |
|||
* @brief Interrupt Service Routines. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© Copyright (c) 2020 STMicroelectronics. |
|||
* All rights reserved.</center></h2> |
|||
* |
|||
* This software component is licensed by ST under BSD 3-Clause license, |
|||
* the "License"; You may not use this file except in compliance with the |
|||
* License. You may obtain a copy of the License at: |
|||
* opensource.org/licenses/BSD-3-Clause |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
/* USER CODE END Header */ |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "main.h" |
|||
#include "stm32f7xx_it.h" |
|||
/* Private includes ----------------------------------------------------------*/ |
|||
/* USER CODE BEGIN Includes */ |
|||
/* USER CODE END Includes */ |
|||
|
|||
/* Private typedef -----------------------------------------------------------*/ |
|||
/* USER CODE BEGIN TD */ |
|||
|
|||
/* USER CODE END TD */ |
|||
|
|||
/* Private define ------------------------------------------------------------*/ |
|||
/* USER CODE BEGIN PD */ |
|||
|
|||
/* USER CODE END PD */ |
|||
|
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/* USER CODE BEGIN PM */ |
|||
|
|||
/* USER CODE END PM */ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* USER CODE BEGIN PV */ |
|||
|
|||
/* USER CODE END PV */ |
|||
|
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
/* USER CODE BEGIN PFP */ |
|||
|
|||
/* USER CODE END PFP */ |
|||
|
|||
/* Private user code ---------------------------------------------------------*/ |
|||
/* USER CODE BEGIN 0 */ |
|||
|
|||
/* USER CODE END 0 */ |
|||
|
|||
/* External variables --------------------------------------------------------*/ |
|||
|
|||
/* USER CODE BEGIN EV */ |
|||
|
|||
/* USER CODE END EV */ |
|||
|
|||
/******************************************************************************/ |
|||
/* Cortex-M7 Processor Interruption and Exception Handlers */ |
|||
/******************************************************************************/ |
|||
/**
|
|||
* @brief This function handles Non maskable interrupt. |
|||
*/ |
|||
void NMI_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ |
|||
|
|||
/* USER CODE END NonMaskableInt_IRQn 0 */ |
|||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */ |
|||
|
|||
/* USER CODE END NonMaskableInt_IRQn 1 */ |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Hard fault interrupt. |
|||
*/ |
|||
void HardFault_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN HardFault_IRQn 0 */ |
|||
|
|||
/* USER CODE END HardFault_IRQn 0 */ |
|||
while (1) |
|||
{ |
|||
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ |
|||
/* USER CODE END W1_HardFault_IRQn 0 */ |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Memory management fault. |
|||
*/ |
|||
void MemManage_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ |
|||
|
|||
/* USER CODE END MemoryManagement_IRQn 0 */ |
|||
while (1) |
|||
{ |
|||
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ |
|||
/* USER CODE END W1_MemoryManagement_IRQn 0 */ |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Pre-fetch fault, memory access fault. |
|||
*/ |
|||
void BusFault_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN BusFault_IRQn 0 */ |
|||
|
|||
/* USER CODE END BusFault_IRQn 0 */ |
|||
while (1) |
|||
{ |
|||
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ |
|||
/* USER CODE END W1_BusFault_IRQn 0 */ |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Undefined instruction or illegal state. |
|||
*/ |
|||
void UsageFault_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN UsageFault_IRQn 0 */ |
|||
|
|||
/* USER CODE END UsageFault_IRQn 0 */ |
|||
while (1) |
|||
{ |
|||
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ |
|||
/* USER CODE END W1_UsageFault_IRQn 0 */ |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles System service call via SWI instruction. |
|||
*/ |
|||
void SVC_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN SVCall_IRQn 0 */ |
|||
|
|||
/* USER CODE END SVCall_IRQn 0 */ |
|||
/* USER CODE BEGIN SVCall_IRQn 1 */ |
|||
|
|||
/* USER CODE END SVCall_IRQn 1 */ |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Debug monitor. |
|||
*/ |
|||
void DebugMon_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ |
|||
|
|||
/* USER CODE END DebugMonitor_IRQn 0 */ |
|||
/* USER CODE BEGIN DebugMonitor_IRQn 1 */ |
|||
|
|||
/* USER CODE END DebugMonitor_IRQn 1 */ |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles Pendable request for system service. |
|||
*/ |
|||
void PendSV_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN PendSV_IRQn 0 */ |
|||
|
|||
/* USER CODE END PendSV_IRQn 0 */ |
|||
/* USER CODE BEGIN PendSV_IRQn 1 */ |
|||
|
|||
/* USER CODE END PendSV_IRQn 1 */ |
|||
} |
|||
|
|||
/**
|
|||
* @brief This function handles System tick timer. |
|||
*/ |
|||
void SysTick_Handler(void) |
|||
{ |
|||
/* USER CODE BEGIN SysTick_IRQn 0 */ |
|||
|
|||
/* USER CODE END SysTick_IRQn 0 */ |
|||
HAL_IncTick(); |
|||
/* USER CODE BEGIN SysTick_IRQn 1 */ |
|||
|
|||
/* USER CODE END SysTick_IRQn 1 */ |
|||
} |
|||
|
|||
/******************************************************************************/ |
|||
/* STM32F7xx Peripheral Interrupt Handlers */ |
|||
/* Add here the Interrupt Handlers for the used peripherals. */ |
|||
/* For the available peripheral interrupt handler names, */ |
|||
/* please refer to the startup file (startup_stm32f7xx.s). */ |
|||
/******************************************************************************/ |
|||
|
|||
/* USER CODE BEGIN 1 */ |
|||
|
|||
/* USER CODE END 1 */ |
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
@ -0,0 +1,244 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file system_stm32f7xx.c |
|||
* @author MCD Application Team |
|||
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. |
|||
* |
|||
* This file provides two functions and one global variable to be called from |
|||
* user application: |
|||
* - SystemInit(): This function is called at startup just after reset and |
|||
* before branch to main program. This call is made inside |
|||
* the "startup_stm32f7xx.s" file. |
|||
* |
|||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
|||
* by the user application to setup the SysTick |
|||
* timer or configure other parameters. |
|||
* |
|||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
|||
* be called whenever the core clock is changed |
|||
* during program execution. |
|||
* |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved.</center></h2> |
|||
* |
|||
* This software component is licensed by ST under BSD 3-Clause license, |
|||
* the "License"; You may not use this file except in compliance with the |
|||
* License. You may obtain a copy of the License at: |
|||
* opensource.org/licenses/BSD-3-Clause |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/** @addtogroup CMSIS
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup stm32f7xx_system
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_Includes
|
|||
* @{ |
|||
*/ |
|||
|
|||
#include "stm32f7xx.h" |
|||
|
|||
#if !defined (HSE_VALUE) |
|||
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
|||
#endif /* HSE_VALUE */ |
|||
|
|||
#if !defined (HSI_VALUE) |
|||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
|||
#endif /* HSI_VALUE */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/************************* Miscellaneous Configuration ************************/ |
|||
|
|||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
|||
Internal SRAM. */ |
|||
/* #define VECT_TAB_SRAM */ |
|||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
|||
This value must be a multiple of 0x200. */ |
|||
/******************************************************************************/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* This variable is updated in three ways:
|
|||
1) by calling CMSIS function SystemCoreClockUpdate() |
|||
2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
|||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
|||
Note: If you use this function to configure the system clock; then there |
|||
is no need to call the 2 first functions listed above, since SystemCoreClock |
|||
variable is updated automatically. |
|||
*/ |
|||
uint32_t SystemCoreClock = 16000000; |
|||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
|||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F7xx_System_Private_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Setup the microcontroller system |
|||
* Initialize the Embedded Flash Interface, the PLL and update the |
|||
* SystemFrequency variable. |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void SystemInit(void) |
|||
{ |
|||
/* FPU settings ------------------------------------------------------------*/ |
|||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
|||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
|||
#endif |
|||
|
|||
/* Configure the Vector Table location add offset address ------------------*/ |
|||
#ifdef VECT_TAB_SRAM |
|||
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
|||
#else |
|||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
|||
#endif |
|||
} |
|||
|
|||
/**
|
|||
* @brief Update SystemCoreClock variable according to Clock Register Values. |
|||
* The SystemCoreClock variable contains the core clock (HCLK), it can |
|||
* be used by the user application to setup the SysTick timer or configure |
|||
* other parameters. |
|||
* |
|||
* @note Each time the core clock (HCLK) changes, this function must be called |
|||
* to update SystemCoreClock variable value. Otherwise, any configuration |
|||
* based on this variable will be incorrect. |
|||
* |
|||
* @note - The system frequency computed by this function is not the real |
|||
* frequency in the chip. It is calculated based on the predefined |
|||
* constant and the selected clock source: |
|||
* |
|||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
|||
* |
|||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
|||
* |
|||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
|||
* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
|||
* |
|||
* (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value |
|||
* 16 MHz) but the real value may vary depending on the variations |
|||
* in voltage and temperature. |
|||
* |
|||
* (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value |
|||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real |
|||
* frequency of the crystal used. Otherwise, this function may |
|||
* have wrong result. |
|||
* |
|||
* - The result of this function could be not correct when using fractional |
|||
* value for HSE crystal. |
|||
* |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void SystemCoreClockUpdate(void) |
|||
{ |
|||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
|||
|
|||
/* Get SYSCLK source -------------------------------------------------------*/ |
|||
tmp = RCC->CFGR & RCC_CFGR_SWS; |
|||
|
|||
switch (tmp) |
|||
{ |
|||
case 0x00: /* HSI used as system clock source */ |
|||
SystemCoreClock = HSI_VALUE; |
|||
break; |
|||
case 0x04: /* HSE used as system clock source */ |
|||
SystemCoreClock = HSE_VALUE; |
|||
break; |
|||
case 0x08: /* PLL used as system clock source */ |
|||
|
|||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
|||
SYSCLK = PLL_VCO / PLL_P |
|||
*/ |
|||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
|||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
|||
|
|||
if (pllsource != 0) |
|||
{ |
|||
/* HSE used as PLL clock source */ |
|||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
|||
} |
|||
else |
|||
{ |
|||
/* HSI used as PLL clock source */ |
|||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
|||
} |
|||
|
|||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
|||
SystemCoreClock = pllvco/pllp; |
|||
break; |
|||
default: |
|||
SystemCoreClock = HSI_VALUE; |
|||
break; |
|||
} |
|||
/* Compute HCLK frequency --------------------------------------------------*/ |
|||
/* Get HCLK prescaler */ |
|||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
|||
/* HCLK frequency */ |
|||
SystemCoreClock >>= tmp; |
|||
} |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
@ -0,0 +1,865 @@ |
|||
/**************************************************************************//**
|
|||
* @file cmsis_armcc.h |
|||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file |
|||
* @version V5.0.4 |
|||
* @date 10. January 2018 |
|||
******************************************************************************/ |
|||
/*
|
|||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0 |
|||
* |
|||
* Licensed under the Apache License, Version 2.0 (the License); you may |
|||
* not use this file except in compliance with the License. |
|||
* You may obtain a copy of the License at |
|||
* |
|||
* www.apache.org/licenses/LICENSE-2.0 |
|||
* |
|||
* Unless required by applicable law or agreed to in writing, software |
|||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
|||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|||
* See the License for the specific language governing permissions and |
|||
* limitations under the License. |
|||
*/ |
|||
|
|||
#ifndef __CMSIS_ARMCC_H |
|||
#define __CMSIS_ARMCC_H |
|||
|
|||
|
|||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
|||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!" |
|||
#endif |
|||
|
|||
/* CMSIS compiler control architecture macros */ |
|||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ |
|||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) |
|||
#define __ARM_ARCH_6M__ 1 |
|||
#endif |
|||
|
|||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) |
|||
#define __ARM_ARCH_7M__ 1 |
|||
#endif |
|||
|
|||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) |
|||
#define __ARM_ARCH_7EM__ 1 |
|||
#endif |
|||
|
|||
/* __ARM_ARCH_8M_BASE__ not applicable */ |
|||
/* __ARM_ARCH_8M_MAIN__ not applicable */ |
|||
|
|||
|
|||
/* CMSIS compiler specific defines */ |
|||
#ifndef __ASM |
|||
#define __ASM __asm |
|||
#endif |
|||
#ifndef __INLINE |
|||
#define __INLINE __inline |
|||
#endif |
|||
#ifndef __STATIC_INLINE |
|||
#define __STATIC_INLINE static __inline |
|||
#endif |
|||
#ifndef __STATIC_FORCEINLINE |
|||
#define __STATIC_FORCEINLINE static __forceinline |
|||
#endif |
|||
#ifndef __NO_RETURN |
|||
#define __NO_RETURN __declspec(noreturn) |
|||
#endif |
|||
#ifndef __USED |
|||
#define __USED __attribute__((used)) |
|||
#endif |
|||
#ifndef __WEAK |
|||
#define __WEAK __attribute__((weak)) |
|||
#endif |
|||
#ifndef __PACKED |
|||
#define __PACKED __attribute__((packed)) |
|||
#endif |
|||
#ifndef __PACKED_STRUCT |
|||
#define __PACKED_STRUCT __packed struct |
|||
#endif |
|||
#ifndef __PACKED_UNION |
|||
#define __PACKED_UNION __packed union |
|||
#endif |
|||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
|||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) |
|||
#endif |
|||
#ifndef __UNALIGNED_UINT16_WRITE |
|||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) |
|||
#endif |
|||
#ifndef __UNALIGNED_UINT16_READ |
|||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) |
|||
#endif |
|||
#ifndef __UNALIGNED_UINT32_WRITE |
|||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) |
|||
#endif |
|||
#ifndef __UNALIGNED_UINT32_READ |
|||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) |
|||
#endif |
|||
#ifndef __ALIGNED |
|||
#define __ALIGNED(x) __attribute__((aligned(x))) |
|||
#endif |
|||
#ifndef __RESTRICT |
|||
#define __RESTRICT __restrict |
|||
#endif |
|||
|
|||
/* ########################### Core Function Access ########################### */ |
|||
/** \ingroup CMSIS_Core_FunctionInterface
|
|||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
|||
@{ |
|||
*/ |
|||
|
|||
/**
|
|||
\brief Enable IRQ Interrupts |
|||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
|||
Can only be executed in Privileged modes. |
|||
*/ |
|||
/* intrinsic void __enable_irq(); */ |
|||
|
|||
|
|||
/**
|
|||
\brief Disable IRQ Interrupts |
|||
\details Disables IRQ interrupts by setting the I-bit in the CPSR. |
|||
Can only be executed in Privileged modes. |
|||
*/ |
|||
/* intrinsic void __disable_irq(); */ |
|||
|
|||
/**
|
|||
\brief Get Control Register |
|||
\details Returns the content of the Control Register. |
|||
\return Control Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_CONTROL(void) |
|||
{ |
|||
register uint32_t __regControl __ASM("control"); |
|||
return(__regControl); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Control Register |
|||
\details Writes the given value to the Control Register. |
|||
\param [in] control Control Register value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_CONTROL(uint32_t control) |
|||
{ |
|||
register uint32_t __regControl __ASM("control"); |
|||
__regControl = control; |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get IPSR Register |
|||
\details Returns the content of the IPSR Register. |
|||
\return IPSR Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_IPSR(void) |
|||
{ |
|||
register uint32_t __regIPSR __ASM("ipsr"); |
|||
return(__regIPSR); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get APSR Register |
|||
\details Returns the content of the APSR Register. |
|||
\return APSR Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_APSR(void) |
|||
{ |
|||
register uint32_t __regAPSR __ASM("apsr"); |
|||
return(__regAPSR); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get xPSR Register |
|||
\details Returns the content of the xPSR Register. |
|||
\return xPSR Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_xPSR(void) |
|||
{ |
|||
register uint32_t __regXPSR __ASM("xpsr"); |
|||
return(__regXPSR); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get Process Stack Pointer |
|||
\details Returns the current value of the Process Stack Pointer (PSP). |
|||
\return PSP Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_PSP(void) |
|||
{ |
|||
register uint32_t __regProcessStackPointer __ASM("psp"); |
|||
return(__regProcessStackPointer); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Process Stack Pointer |
|||
\details Assigns the given value to the Process Stack Pointer (PSP). |
|||
\param [in] topOfProcStack Process Stack Pointer value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
|||
{ |
|||
register uint32_t __regProcessStackPointer __ASM("psp"); |
|||
__regProcessStackPointer = topOfProcStack; |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get Main Stack Pointer |
|||
\details Returns the current value of the Main Stack Pointer (MSP). |
|||
\return MSP Register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_MSP(void) |
|||
{ |
|||
register uint32_t __regMainStackPointer __ASM("msp"); |
|||
return(__regMainStackPointer); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Main Stack Pointer |
|||
\details Assigns the given value to the Main Stack Pointer (MSP). |
|||
\param [in] topOfMainStack Main Stack Pointer value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
|||
{ |
|||
register uint32_t __regMainStackPointer __ASM("msp"); |
|||
__regMainStackPointer = topOfMainStack; |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get Priority Mask |
|||
\details Returns the current state of the priority mask bit from the Priority Mask Register. |
|||
\return Priority Mask value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_PRIMASK(void) |
|||
{ |
|||
register uint32_t __regPriMask __ASM("primask"); |
|||
return(__regPriMask); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Priority Mask |
|||
\details Assigns the given value to the Priority Mask Register. |
|||
\param [in] priMask Priority Mask |
|||
*/ |
|||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
|||
{ |
|||
register uint32_t __regPriMask __ASM("primask"); |
|||
__regPriMask = (priMask); |
|||
} |
|||
|
|||
|
|||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
|||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) |
|||
|
|||
/**
|
|||
\brief Enable FIQ |
|||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
|||
Can only be executed in Privileged modes. |
|||
*/ |
|||
#define __enable_fault_irq __enable_fiq |
|||
|
|||
|
|||
/**
|
|||
\brief Disable FIQ |
|||
\details Disables FIQ interrupts by setting the F-bit in the CPSR. |
|||
Can only be executed in Privileged modes. |
|||
*/ |
|||
#define __disable_fault_irq __disable_fiq |
|||
|
|||
|
|||
/**
|
|||
\brief Get Base Priority |
|||
\details Returns the current value of the Base Priority register. |
|||
\return Base Priority register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_BASEPRI(void) |
|||
{ |
|||
register uint32_t __regBasePri __ASM("basepri"); |
|||
return(__regBasePri); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Base Priority |
|||
\details Assigns the given value to the Base Priority register. |
|||
\param [in] basePri Base Priority value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
|||
{ |
|||
register uint32_t __regBasePri __ASM("basepri"); |
|||
__regBasePri = (basePri & 0xFFU); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Base Priority with condition |
|||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
|||
or the new value increases the BASEPRI priority level. |
|||
\param [in] basePri Base Priority value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
|||
{ |
|||
register uint32_t __regBasePriMax __ASM("basepri_max"); |
|||
__regBasePriMax = (basePri & 0xFFU); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Get Fault Mask |
|||
\details Returns the current value of the Fault Mask register. |
|||
\return Fault Mask register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_FAULTMASK(void) |
|||
{ |
|||
register uint32_t __regFaultMask __ASM("faultmask"); |
|||
return(__regFaultMask); |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set Fault Mask |
|||
\details Assigns the given value to the Fault Mask register. |
|||
\param [in] faultMask Fault Mask value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
|||
{ |
|||
register uint32_t __regFaultMask __ASM("faultmask"); |
|||
__regFaultMask = (faultMask & (uint32_t)1U); |
|||
} |
|||
|
|||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
|||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ |
|||
|
|||
|
|||
/**
|
|||
\brief Get FPSCR |
|||
\details Returns the current value of the Floating Point Status/Control register. |
|||
\return Floating Point Status/Control register value |
|||
*/ |
|||
__STATIC_INLINE uint32_t __get_FPSCR(void) |
|||
{ |
|||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
|||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
|||
register uint32_t __regfpscr __ASM("fpscr"); |
|||
return(__regfpscr); |
|||
#else |
|||
return(0U); |
|||
#endif |
|||
} |
|||
|
|||
|
|||
/**
|
|||
\brief Set FPSCR |
|||
\details Assigns the given value to the Floating Point Status/Control register. |
|||
\param [in] fpscr Floating Point Status/Control value to set |
|||
*/ |
|||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
|||
{ |
|||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
|||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
|||
register uint32_t __regfpscr __ASM("fpscr"); |
|||
__regfpscr = (fpscr); |
|||
#else |
|||
(void)fpscr; |
|||
#endif |
|||
} |
|||
|
|||
|
|||
/*@} end of CMSIS_Core_RegAccFunctions */ |
|||
|
|||
|
|||
/* ########################## Core Instruction Access ######################### */ |
|||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
|||
Access to dedicated instructions |
|||
@{ |
|||
*/ |
|||
|
|||
/**
|
|||
\brief No Operation |
|||
\details No Operation does nothing. This instruction can be used for code alignment purposes. |
|||
*/ |
|||
#define __NOP __nop |
|||
|
|||
|
|||
/**
|
|||
\brief Wait For Interrupt |
|||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
|||
*/ |
|||
#define __WFI __wfi |
|||
|
|||
|
|||
/**
|
|||
\brief Wait For Event |
|||
\details Wait For Event is a hint instruction that permits the processor to enter |
|||
a low-power state until one of a number of events occurs. |
|||
*/ |
|||
#define __WFE __wfe |
|||
|
|||
|
|||
/**
|
|||
\brief Send Event |
|||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
|||
*/ |
|||
#define __SEV __sev |
|||
|
|||
|
|||
/**
|
|||
\brief Instruction Synchronization Barrier |
|||
\details Instruction Synchronization Barrier flushes the pipeline in the processor, |
|||
so that all instructions following the ISB are fetched from cache or memory, |
|||
after the instruction has been completed. |
|||
*/ |
|||
#define __ISB() do {\ |
|||
__schedule_barrier();\ |
|||
__isb(0xF);\ |
|||
__schedule_barrier();\ |
|||
} while (0U) |
|||
|
|||
/**
|
|||
\brief Data Synchronization Barrier |
|||
\details Acts as a special kind of Data Memory Barrier. |
|||
It completes when all explicit memory accesses before this instruction complete. |
|||
*/ |
|||
#define __DSB() do {\ |
|||
__schedule_barrier();\ |
|||
__dsb(0xF);\ |
|||
__schedule_barrier();\ |
|||
} while (0U) |
|||
|
|||
/**
|
|||
\brief Data Memory Barrier |
|||
\details Ensures the apparent order of the explicit memory operations before |
|||
and after the instruction, without ensuring their completion. |
|||
*/ |
|||
#define __DMB() do {\ |
|||
__schedule_barrier();\ |
|||
__dmb(0xF);\ |
|||
__schedule_barrier();\ |
|||
} while (0U) |
|||
|
|||
|
|||
/**
|
|||
\brief Reverse byte order (32 bit) |
|||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. |
|||
\param [in] value Value to reverse |
|||
\return Reversed value |
|||
*/ |
|||
#define __REV __rev |
|||
|
|||
|
|||
/**
|
|||
\brief Reverse byte order (16 bit) |
|||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. |
|||
\param [in] value Value to reverse |
|||
\return Reversed value |
|||
*/ |
|||
#ifndef __NO_EMBEDDED_ASM |
|||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
|||
{ |
|||
rev16 r0, r0 |
|||
bx lr |
|||
} |
|||
#endif |
|||
|
|||
|
|||
/**
|
|||
\brief Reverse byte order (16 bit) |
|||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. |
|||
\param [in] value Value to reverse |
|||
\return Reversed value |
|||
*/ |
|||
#ifndef __NO_EMBEDDED_ASM |
|||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) |
|||
{ |
|||
revsh r0, r0 |
|||
bx lr |
|||
} |
|||
#endif |
|||
|
|||
|
|||
/**
|
|||
\brief Rotate Right in unsigned value (32 bit) |
|||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
|||
\param [in] op1 Value to rotate |
|||
\param [in] op2 Number of Bits to rotate |
|||
\return Rotated value |
|||
*/ |
|||
#define __ROR __ror |
|||
|
|||
|
|||
/**
|
|||
\brief Breakpoint |
|||