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Merge with tobster things

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squeaky otter 2 years ago
parent
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ce21c18e8a
Signed by: dashie GPG Key ID: C2D57B325840B755
  1. 6
      CPLDs/DRAM_altera/.gitignore
  2. 405
      CPLDs/DRAM_altera/T030_DRAM.bdf
  3. 30
      CPLDs/DRAM_altera/T030_DRAM.qpf
  4. 117
      CPLDs/DRAM_altera/T030_DRAM.qsf
  5. 41
      CPLDs/DRAM_altera/T030_DRAM.sdc
  6. 134
      CPLDs/DRAM_altera/dram_ctrl.bsf
  7. 325
      CPLDs/DRAM_altera/dram_ctrl.vhd
  8. 6
      CPLDs/GLUE_altera/.gitignore
  9. 1864
      CPLDs/GLUE_altera/T030_Glue.bdf
  10. 30
      CPLDs/GLUE_altera/T030_Glue.qpf
  11. 125
      CPLDs/GLUE_altera/T030_Glue.qsf
  12. 41
      CPLDs/GLUE_altera/T030_Glue.sdc
  13. 50
      CPLDs/GLUE_altera/clkdiv5.bsf
  14. 82
      CPLDs/GLUE_altera/clkdiv5.vhd
  15. 50
      CPLDs/GLUE_altera/clkdiv7.bsf
  16. 82
      CPLDs/GLUE_altera/clkdiv7.vhd
  17. 218
      CPLDs/GLUE_altera/t030glue.bsf
  18. 111
      CPLDs/GLUE_altera/t030glue.vhd
  19. 50
      CPLDs/GLUE_altera/timer_tick.bsf
  20. 35
      CPLDs/GLUE_altera/timer_tick.vhd
  21. 4
      README.md
  22. 0
      assets/T030_glue_17.jpg
  23. 0
      assets/dram_ctrl_01.vhd
  24. 2
      bios/Makefile

6
CPLDs/DRAM_altera/.gitignore

@ -0,0 +1,6 @@
*.bak
*.qws
db
incremental_db
output_files
simulation

405
CPLDs/DRAM_altera/T030_DRAM.bdf

@ -0,0 +1,405 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 376 224 544 240)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "CLK" (rect 5 0 26 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 240 376 256))
)
(pin
(input)
(rect 376 240 544 256)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "CS" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 256 376 272))
)
(pin
(input)
(rect 376 256 544 272)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "RESET" (rect 5 0 40 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 272 376 288))
)
(pin
(input)
(rect 376 272 544 288)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "RW" (rect 5 0 23 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 288 376 304))
)
(pin
(input)
(rect 376 288 544 304)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "SIZ0" (rect 5 0 28 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 304 376 320))
)
(pin
(input)
(rect 376 304 544 320)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "SIZ1" (rect 5 0 28 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 320 376 336))
)
(pin
(input)
(rect 376 320 544 336)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "A[25..0]" (rect 5 0 44 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 336 376 352))
)
(pin
(input)
(rect 376 424 544 440)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "AS" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 712 240 888 256)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "RAS" (rect 90 0 112 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 256 936 272))
)
(pin
(output)
(rect 712 256 888 272)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "CAS0" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 272 936 288))
)
(pin
(output)
(rect 712 272 888 288)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "CAS1" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 288 936 304))
)
(pin
(output)
(rect 712 288 888 304)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "CAS2" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 304 936 320))
)
(pin
(output)
(rect 712 304 888 320)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "CAS3" (rect 90 0 118 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 320 936 336))
)
(pin
(output)
(rect 712 320 888 336)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "WE" (rect 90 0 107 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 336 936 352))
)
(pin
(output)
(rect 712 224 888 240)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "DTACK" (rect 90 0 126 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 240 936 256))
)
(pin
(output)
(rect 712 336 888 352)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "MA[11..0]" (rect 90 0 137 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 888 352 936 368))
)
(symbol
(rect 544 200 712 376)
(text "dram_ctrl" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 160 25 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "cs" (rect 0 0 11 12)(font "Arial" ))
(text "cs" (rect 21 43 32 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "reset" (rect 0 0 24 12)(font "Arial" ))
(text "reset" (rect 21 59 45 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "rw" (rect 0 0 10 12)(font "Arial" ))
(text "rw" (rect 21 75 31 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "siz0" (rect 0 0 18 12)(font "Arial" ))
(text "siz0" (rect 21 91 39 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "siz1" (rect 0 0 18 12)(font "Arial" ))
(text "siz1" (rect 21 107 39 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "a[25..0]" (rect 0 0 37 12)(font "Arial" ))
(text "a[25..0]" (rect 21 123 58 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "dtack" (rect 0 0 27 12)(font "Arial" ))
(text "dtack" (rect 125 27 152 39)(font "Arial" ))
(line (pt 168 32)(pt 152 32))
)
(port
(pt 168 48)
(output)
(text "ras" (rect 0 0 15 12)(font "Arial" ))
(text "ras" (rect 135 43 150 55)(font "Arial" ))
(line (pt 168 48)(pt 152 48))
)
(port
(pt 168 64)
(output)
(text "cas0" (rect 0 0 23 12)(font "Arial" ))
(text "cas0" (rect 128 59 151 71)(font "Arial" ))
(line (pt 168 64)(pt 152 64))
)
(port
(pt 168 80)
(output)
(text "cas1" (rect 0 0 23 12)(font "Arial" ))
(text "cas1" (rect 128 75 151 87)(font "Arial" ))
(line (pt 168 80)(pt 152 80))
)
(port
(pt 168 96)
(output)
(text "cas2" (rect 0 0 23 12)(font "Arial" ))
(text "cas2" (rect 128 91 151 103)(font "Arial" ))
(line (pt 168 96)(pt 152 96))
)
(port
(pt 168 112)
(output)
(text "cas3" (rect 0 0 23 12)(font "Arial" ))
(text "cas3" (rect 128 107 151 119)(font "Arial" ))
(line (pt 168 112)(pt 152 112))
)
(port
(pt 168 128)
(output)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 137 123 149 135)(font "Arial" ))
(line (pt 168 128)(pt 152 128))
)
(port
(pt 168 144)
(output)
(text "ma[11..0]" (rect 0 0 47 12)(font "Arial" ))
(text "ma[11..0]" (rect 108 139 155 151)(font "Arial" ))
(line (pt 168 144)(pt 152 144)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 160))
)
)

30
CPLDs/DRAM_altera/T030_DRAM.qpf

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 15:06:31 April 27, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "15:06:31 April 27, 2016"
# Revisions
PROJECT_REVISION = "T030_DRAM"

117
CPLDs/DRAM_altera/T030_DRAM.qsf

@ -0,0 +1,117 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 15:06:31 April 27, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# T030_DRAM_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY T030_DRAM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:06:31 APRIL 27, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name VHDL_FILE dram_ctrl.vhd
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name BDF_FILE T030_DRAM.bdf
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_global_assignment -name SDC_FILE T030_DRAM.sdc
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_location_assignment PIN_36 -to CS
set_location_assignment PIN_35 -to RW
set_location_assignment PIN_58 -to CAS0
set_location_assignment PIN_60 -to CAS1
set_location_assignment PIN_61 -to CAS2
set_location_assignment PIN_63 -to CAS3
set_location_assignment PIN_83 -to CLK
set_location_assignment PIN_64 -to RAS
set_location_assignment PIN_65 -to WE
set_location_assignment PIN_81 -to RESET
set_global_assignment -name VECTOR_WAVEFORM_FILE RAM_access.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Refresh.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE RAM_write.vwf
set_location_assignment PIN_12 -to A[0]
set_location_assignment PIN_11 -to A[1]
set_location_assignment PIN_10 -to A[2]
set_location_assignment PIN_9 -to A[3]
set_location_assignment PIN_8 -to A[4]
set_location_assignment PIN_6 -to A[5]
set_location_assignment PIN_5 -to A[6]
set_location_assignment PIN_4 -to A[7]
set_location_assignment PIN_22 -to A[8]
set_location_assignment PIN_21 -to A[9]
set_location_assignment PIN_20 -to A[10]
set_location_assignment PIN_18 -to A[11]
set_location_assignment PIN_17 -to A[12]
set_location_assignment PIN_16 -to A[13]
set_location_assignment PIN_15 -to A[14]
set_location_assignment PIN_31 -to A[15]
set_location_assignment PIN_30 -to A[16]
set_location_assignment PIN_29 -to A[17]
set_location_assignment PIN_28 -to A[18]
set_location_assignment PIN_27 -to A[19]
set_location_assignment PIN_25 -to A[20]
set_location_assignment PIN_24 -to A[21]
set_location_assignment PIN_41 -to A[22]
set_location_assignment PIN_40 -to A[23]
set_location_assignment PIN_56 -to MA[10]
set_location_assignment PIN_55 -to MA[9]
set_location_assignment PIN_54 -to MA[8]
set_location_assignment PIN_52 -to MA[7]
set_location_assignment PIN_51 -to MA[6]
set_location_assignment PIN_50 -to MA[5]
set_location_assignment PIN_49 -to MA[4]
set_location_assignment PIN_48 -to MA[3]
set_location_assignment PIN_46 -to MA[2]
set_location_assignment PIN_45 -to MA[1]
set_location_assignment PIN_44 -to MA[0]
set_location_assignment PIN_34 -to SIZ0
set_location_assignment PIN_33 -to SIZ1
set_location_assignment PIN_79 -to DTACK
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/tra/Documents/Altera/T030_DRAM/RAM_access.vwf"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_location_assignment PIN_37 -to A[25]
set_location_assignment PIN_39 -to A[24]
set_location_assignment PIN_57 -to MA[11]

41
CPLDs/DRAM_altera/T030_DRAM.sdc

@ -0,0 +1,41 @@
#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
#
#************************************************************
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "CLK" -period 40.000ns [get_ports {CLK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family MAX7000S
# tsu/th constraints
# tco constraints
# tpd constraints

134
CPLDs/DRAM_altera/dram_ctrl.bsf

@ -0,0 +1,134 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 184 192)
(text "dram_ctrl" (rect 5 0 43 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "cs" (rect 0 0 9 12)(font "Arial" ))
(text "cs" (rect 21 43 30 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "reset" (rect 0 0 20 12)(font "Arial" ))
(text "reset" (rect 21 59 41 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "rw" (rect 0 0 9 12)(font "Arial" ))
(text "rw" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "siz0" (rect 0 0 14 12)(font "Arial" ))
(text "siz0" (rect 21 91 35 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "siz1" (rect 0 0 12 12)(font "Arial" ))
(text "siz1" (rect 21 107 33 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "a[25..0]" (rect 0 0 29 12)(font "Arial" ))
(text "a[25..0]" (rect 21 123 50 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "dtack" (rect 0 0 21 12)(font "Arial" ))
(text "dtack" (rect 126 27 147 39)(font "Arial" ))
(line (pt 168 32)(pt 152 32)(line_width 1))
)
(port
(pt 168 48)
(output)
(text "ras" (rect 0 0 12 12)(font "Arial" ))
(text "ras" (rect 135 43 147 55)(font "Arial" ))
(line (pt 168 48)(pt 152 48)(line_width 1))
)
(port
(pt 168 64)
(output)
(text "cas0" (rect 0 0 18 12)(font "Arial" ))
(text "cas0" (rect 129 59 147 71)(font "Arial" ))
(line (pt 168 64)(pt 152 64)(line_width 1))
)
(port
(pt 168 80)
(output)
(text "cas1" (rect 0 0 17 12)(font "Arial" ))
(text "cas1" (rect 130 75 147 87)(font "Arial" ))
(line (pt 168 80)(pt 152 80)(line_width 1))
)
(port
(pt 168 96)
(output)
(text "cas2" (rect 0 0 18 12)(font "Arial" ))
(text "cas2" (rect 129 91 147 103)(font "Arial" ))
(line (pt 168 96)(pt 152 96)(line_width 1))
)
(port
(pt 168 112)
(output)
(text "cas3" (rect 0 0 18 12)(font "Arial" ))
(text "cas3" (rect 129 107 147 119)(font "Arial" ))
(line (pt 168 112)(pt 152 112)(line_width 1))
)
(port
(pt 168 128)
(output)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 137 123 147 135)(font "Arial" ))
(line (pt 168 128)(pt 152 128)(line_width 1))
)
(port
(pt 168 144)
(output)
(text "ma[11..0]" (rect 0 0 35 12)(font "Arial" ))
(text "ma[11..0]" (rect 112 139 147 151)(font "Arial" ))
(line (pt 168 144)(pt 152 144)(line_width 3))
)
(drawing
(rectangle (rect 16 16 152 160)(line_width 1))
)
)

325
CPLDs/DRAM_altera/dram_ctrl.vhd

@ -0,0 +1,325 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY dram_ctrl IS PORT(
clk : IN std_logic; -- Clock
cs : IN std_logic; -- Chip select
reset : IN std_logic; -- Reset signal
rw : IN std_logic; -- Processor Read/Write signal
siz0, siz1 : IN std_logic; -- Data size from CPU
a : IN std_logic_vector(25 downto 0); -- Processor address lines
dtack : OUT std_logic; -- Data ack signal to CPU
ras : OUT std_logic; -- DRAM RAS signal
cas0,cas1,cas2,cas3 : OUT std_logic; -- DRAM CAS signals
we : OUT std_logic; -- DRAM write enable signal
ma : OUT std_logic_vector(11 downto 0)); -- DRAM address lines
END dram_ctrl;
ARCHITECTURE behavioral OF dram_ctrl IS
-- Asynchronous versions of outputs to be synchronized to clk in the syncronous process
SIGNAL ras_a : std_logic;
SIGNAL cas0_a, cas1_a, cas2_a, cas3_a : std_logic;
SIGNAL dtack_a : std_logic;
SIGNAL we_a, ref_ack_a, mux_a : std_logic;
-- Other internal signals
SIGNAL ref_req : std_logic; -- Refresh request
SIGNAL tc : std_logic; -- Refresh counter terminal count signal
SIGNAL q : std_logic_vector(8 downto 0); -- The refresh counter
SIGNAL ref_ack : std_logic; -- Refresh ack
SIGNAL ps, ns : std_logic_vector(3 downto 0); -- Prev/next state
SIGNAL mux : std_logic; -- Mux signal
SIGNAL caswr : std_logic_vector(3 downto 0); -- CAS vector for write
-- State declarations
CONSTANT idle : std_logic_vector(3 downto 0) := "0000";
CONSTANT rw1 : std_logic_vector(3 downto 0) := "0001";
CONSTANT rw1x : std_logic_vector(3 downto 0) := "1010";
CONSTANT rw2 : std_logic_vector(3 downto 0) := "0011";
CONSTANT rw3 : std_logic_vector(3 downto 0) := "0010";
CONSTANT rw3x : std_logic_vector(3 downto 0) := "1110";
CONSTANT cbr1 : std_logic_vector(3 downto 0) := "0111";
CONSTANT cbr2 : std_logic_vector(3 downto 0) := "0101";
CONSTANT cbr3 : std_logic_vector(3 downto 0) := "0100";
CONSTANT cbr3x : std_logic_vector(3 downto 0) := "1011";
CONSTANT cbr4 : std_logic_vector(3 downto 0) := "1000";
CONSTANT prechg : std_logic_vector(3 downto 0) := "1001";
BEGIN
-- The DRAM controller state machine is implemented as a two-process FSM.
-- The first process is the asynchronous one that determines the next state
-- based upon current state and other inputs. Internal control signal levels
-- are also set in this rocess.
-- The second process is a small synchronous process that synchronizes the
-- state transitions and control signal outputs to the system clock.
-- Address mux
ma <= a(13 downto 2) WHEN mux = '1' ELSE a(25 downto 14);
-- Transfer LUT
caswr <= "0111" WHEN siz1 = '0' AND siz0 = '1' AND a(1) = '0' AND a(0) = '0' ELSE
"1011" WHEN siz1 = '0' AND siz0 = '1' AND a(1) = '0' AND a(0) = '1' ELSE
"1101" WHEN siz1 = '0' AND siz0 = '1' AND a(1) = '1' AND a(0) = '0' ELSE
"1110" WHEN siz1 = '0' AND siz0 = '1' AND a(1) = '1' AND a(0) = '1' ELSE
"0011" WHEN siz1 = '1' AND siz0 = '0' AND a(1) = '0' AND a(0) = '0' ELSE
"1001" WHEN siz1 = '1' AND siz0 = '0' AND a(1) = '0' AND a(0) = '1' ELSE
"1100" WHEN siz1 = '1' AND siz0 = '0' AND a(1) = '1' AND a(0) = '0' ELSE
"1110" WHEN siz1 = '1' AND siz0 = '0' AND a(1) = '1' AND a(0) = '1' ELSE
"0001" WHEN siz1 = '1' AND siz0 = '1' AND a(1) = '0' AND a(0) = '0' ELSE
"1000" WHEN siz1 = '1' AND siz0 = '1' AND a(1) = '0' AND a(0) = '1' ELSE
"1100" WHEN siz1 = '1' AND siz0 = '1' AND a(1) = '1' AND a(0) = '0' ELSE
"1110" WHEN siz1 = '1' AND siz0 = '1' AND a(1) = '1' AND a(0) = '1' ELSE
"0000" WHEN siz1 = '0' AND siz0 = '0' AND a(1) = '0' AND a(0) = '0' ELSE
"1000" WHEN siz1 = '0' AND siz0 = '0' AND a(1) = '0' AND a(0) = '1' ELSE
"1100" WHEN siz1 = '0' AND siz0 = '0' AND a(1) = '1' AND a(0) = '0' ELSE
"1110" WHEN siz1 = '0' AND siz0 = '0' AND a(1) = '1' AND a(0) = '1' ELSE
"1111";
---------------------------------------
------ Asynchronous process -----------
---------------------------------------
PROCESS (cs, ref_req, ps, rw, caswr)
BEGIN
CASE ps IS
WHEN idle =>
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
mux_a <= '0';
we_a <= rw;
IF (ref_req = '1') THEN
ns <= cbr1; -- do a refresh cycle
we_a <= '1';
dtack_a <= '1';
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
mux_a <= '0';
ELSIF (cs = '0') THEN
ns <= rw1; -- do a normal read/write cycle
we_a <= rw;
dtack_a <= '1';
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
mux_a <= '1';
ELSE
ns <= idle; -- continue to idle
we_a <= '1';
dtack_a <= '1';
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
mux_a <= '0';
END IF;
WHEN rw1 => -- DRAM access start
ras_a <= '0'; -- RAS active
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
mux_a <= '1';
we_a <= rw;
ns <= rw1x;
WHEN rw1x =>
ras_a <= '0'; -- RAS active
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
mux_a <= '0';
we_a <= rw;
ns <= rw2;
WHEN rw2 =>
ras_a <= '0';
IF (rw = '1') THEN
cas0_a <= '0'; -- CAS active
cas1_a <= '0';
cas2_a <= '0';
cas3_a <= '0';
ELSE
cas0_a <= caswr(0);
cas1_a <= caswr(1);
cas2_a <= caswr(2);
cas3_a <= caswr(3);
END IF;
dtack_a <= '0';
mux_a <= '0';
ref_ack_a <= '0';
we_a <= rw;
ns <= rw3;
WHEN rw3 =>
ras_a <= '1';
IF (rw = '1') THEN
cas0_a <= '0'; -- CAS active
cas1_a <= '0';
cas2_a <= '0';
cas3_a <= '0';
ELSE
cas0_a <= caswr(0);
cas1_a <= caswr(1);
cas2_a <= caswr(2);
cas3_a <= caswr(3);
END IF;
dtack_a <= '1';
ref_ack_a <= '0';
mux_a <= '0';
we_a <= '1';
ns <= prechg;
WHEN cbr1 => -- CBR mode start
ras_a <= '1';
cas0_a <= '0'; -- start with CAS
cas1_a <= '0';
cas2_a <= '0';
cas3_a <= '0';
dtack_a <= '1';
ref_ack_a <= '1'; --refresh request register clear
we_a <= '1'; --refresh mode
mux_a <= '0';
ns <= cbr2;
WHEN cbr2 =>
ras_a <= '0'; -- then RAS
cas0_a <= '0';
cas1_a <= '0';
cas2_a <= '0';
cas3_a <= '0';
dtack_a <= '1';
ref_ack_a <= '0';
we_a <= '1';
mux_a <= '0';
ns <= cbr3;
WHEN cbr3 =>
ras_a <= '0';
cas0_a <= '1'; -- deassert CAS
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
we_a <= '1';
mux_a <= '0';
ns <= cbr4;
WHEN cbr4 =>
ras_a <= '1'; -- deassert RAS
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
we_a <= '1';
mux_a <= '0';
ns <= prechg;
WHEN prechg =>
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
we_a <= '1';
mux_a <= '0';
ns <= idle;
WHEN OTHERS =>
ras_a <= '1';
cas0_a <= '1';
cas1_a <= '1';
cas2_a <= '1';
cas3_a <= '1';
dtack_a <= '1';
ref_ack_a <= '0';
mux_a <= '0';
we_a <= rw;
ns <= idle;
END CASE;
END PROCESS;
---------------------------------------------
-------- Synchronous Process ---------------
---------------------------------------------
PROCESS (clk, reset)
BEGIN
IF (reset = '0') THEN
ps <= idle;
ras <= '1';
cas0 <= '1';
cas1 <= '1';
cas2 <= '1';
cas3 <= '1';
dtack <= '1';
we <= '1';
ref_ack <= '0';
ELSIF (clk'event AND clk = '0') THEN -- state machine clocked on falling edge
ps <= ns; -- update the state machine state
ras <= ras_a; -- and assert the synchronous outputs
cas0 <= cas0_a;
cas1 <= cas1_a;
cas2 <= cas2_a;
cas3 <= cas3_a;
dtack <= dtack_a;
we <= we_a;
ref_ack <= ref_ack_a;
mux <= mux_a;
END IF;
END PROCESS;
---------------------------------------
---- Refresh counter
---- 9bits 15.6us interval
---------------------------------------
PROCESS (clk, ref_ack, reset)
BEGIN
IF (reset = '0') THEN
q <= "000000000";
ELSIF (clk'event AND clk = '0') THEN
IF (ref_ack = '1') THEN
q <= "000000000";
ELSE
q <= q + 1;
END IF;
END IF;
END PROCESS;
-- 186hex = 110000110 binary = 390 decimal
-- assuming 25 MHz clock (40ns clock period)
-- 40ns (tCYC) x 390 = 15.6us is the refresh request rate.
tc <= '1' WHEN q = "110000110" ELSE '0';
PROCESS (clk, tc, ref_ack, reset)
BEGIN
IF (reset = '0') THEN
ref_req <= '0';
ELSIF (clk'event AND clk = '0') THEN
IF ref_ack = '1' THEN
ref_req <= '0';
ELSIF tc = '1' THEN -- assert refreq when the terminal count (tc) is reached
ref_req <= '1';
END IF;
END IF;
END PROCESS;
END behavioral;

6
CPLDs/GLUE_altera/.gitignore

@ -0,0 +1,6 @@
*.bak
*.qws
db
incremental_db
output_files
simulation

1864
CPLDs/GLUE_altera/T030_Glue.bdf

File diff suppressed because it is too large

30
CPLDs/GLUE_altera/T030_Glue.qpf

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 10:38:58 July 06, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "10:38:58 July 06, 2018"
# Revisions
PROJECT_REVISION = "T030_Glue"

125
CPLDs/GLUE_altera/T030_Glue.qsf

@ -0,0 +1,125 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 10:38:58 July 06, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# T030_Glue_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY T030_Glue
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:38:58 JULY 06, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_10 -to RESET
set_location_assignment PIN_4 -to AS
set_location_assignment PIN_44 -to AUX0
set_location_assignment PIN_45 -to AUX1
set_location_assignment PIN_46 -to AUX2
set_location_assignment PIN_48 -to AUX3
set_location_assignment PIN_49 -to AUX4
set_location_assignment PIN_50 -to AUX5
set_location_assignment PIN_12 -to AVEC
set_location_assignment PIN_15 -to BERR
set_location_assignment PIN_22 -to CIIN
set_location_assignment PIN_11 -to CPUCLK
set_location_assignment PIN_80 -to DRAMCLK
set_location_assignment PIN_79 -to DRAMCS
set_location_assignment PIN_81 -to DRAMDTACK
set_location_assignment PIN_5 -to DS
set_location_assignment PIN_55 -to IDE_CS0
set_location_assignment PIN_56 -to IDE_CS1
set_location_assignment PIN_52 -to IDE_DTACK
set_location_assignment PIN_51 -to IDE_IRQ
set_location_assignment PIN_54 -to IDE_RD
set_location_assignment PIN_57 -to IDE_WR
set_location_assignment PIN_35 -to IPL0
set_location_assignment PIN_34 -to IPL1
set_location_assignment PIN_33 -to IPL2
set_location_assignment PIN_65 -to MFPCLK
set_location_assignment PIN_67 -to MFPCS
set_location_assignment PIN_69 -to MFPDTACK
set_location_assignment PIN_68 -to MFPIACK
set_location_assignment PIN_70 -to MFPIRQ
set_location_assignment PIN_64 -to RAMCE
set_location_assignment PIN_63 -to ROMCE
set_location_assignment PIN_17 -to SIZ0
set_location_assignment PIN_16 -to SIZ1
set_location_assignment PIN_76 -to SPICLK
set_location_assignment PIN_74 -to SPICS
set_location_assignment PIN_75 -to SPIDS
set_location_assignment PIN_77 -to SPIIRQ
set_location_assignment PIN_9 -to STERM
set_location_assignment PIN_18 -to fc[2]
set_location_assignment PIN_20 -to fc[1]
set_location_assignment PIN_21 -to fc[0]
set_location_assignment PIN_73 -to BUFCE
set_global_assignment -name VECTOR_WAVEFORM_FILE TEST.vwf
set_global_assignment -name VHDL_FILE t030glue.vhd
set_global_assignment -name VHDL_FILE clkdiv5.vhd
set_global_assignment -name VHDL_FILE clkdiv7.vhd
set_global_assignment -name BDF_FILE T030_Glue.bdf
set_global_assignment -name SDC_FILE T030_Glue.sdc
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_location_assignment PIN_36 -to ah[26]
set_location_assignment PIN_37 -to ah[25]
set_location_assignment PIN_39 -to ah[24]
set_location_assignment PIN_40 -to ah[23]
set_location_assignment PIN_41 -to ah[22]
set_location_assignment PIN_24 -to ah[21]
set_location_assignment PIN_25 -to ah[20]
set_location_assignment PIN_27 -to ah[19]
set_location_assignment PIN_28 -to al[3]
set_location_assignment PIN_29 -to al[2]
set_location_assignment PIN_30 -to al[1]
set_location_assignment PIN_31 -to al[0]
set_location_assignment PIN_6 -to dsack[1]
set_location_assignment PIN_8 -to dsack[0]
set_location_assignment PIN_61 -to ide_a[2]
set_location_assignment PIN_60 -to ide_a[1]
set_location_assignment PIN_58 -to ide_a[0]
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
set_global_assignment -name VHDL_FILE timer_tick.vhd
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/tra/Documents/Altera/t030_glue_altera/TEST.vwf"

41
CPLDs/GLUE_altera/T030_Glue.sdc

@ -0,0 +1,41 @@
#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
#
#************************************************************
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "CLK" -period 40.000ns [get_ports {CLK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family MAX7000S
# tsu/th constraints
# tco constraints
# tpd constraints

50
CPLDs/GLUE_altera/clkdiv5.bsf

@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 96)
(text "clkdiv5" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "reset_n" (rect 0 0 30 12)(font "Arial" ))
(text "reset_n" (rect 21 27 51 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "clkin" (rect 0 0 16 12)(font "Arial" ))
(text "clkin" (rect 21 43 37 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "clkout" (rect 0 0 22 12)(font "Arial" ))
(text "clkout" (rect 109 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 64)(line_width 1))
)
)

82
CPLDs/GLUE_altera/clkdiv5.vhd

@ -0,0 +1,82 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY clkdiv5 IS
PORT
(
reset_n : IN STD_LOGIC;
clkin : IN STD_LOGIC;
clkout : OUT STD_LOGIC
);
END clkdiv5;
ARCHITECTURE arch OF clkdiv5 IS
SIGNAL COUNTER : UNSIGNED(2 DOWNTO 0);
SIGNAL div_1 : STD_LOGIC;
SIGNAL div_2 : STD_LOGIC;
SIGNAL clk_low_cnt : STD_LOGIC;
SIGNAL clk_high_cnt : STD_LOGIC;
BEGIN
-- Counter generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
COUNTER <= "111";
ELSIF RISING_EDGE(clkin) THEN
IF COUNTER = "100" THEN
COUNTER <= "000";
ELSE
COUNTER <= COUNTER + 1;
END IF;
END IF;
END PROCESS;
-- clk_r generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
clk_low_cnt <= '0';
clk_high_cnt <= '0';
ELSIF RISING_EDGE(clkin) THEN
IF COUNTER = "000" THEN
clk_low_cnt <= '1';
ELSE
clk_low_cnt <= '0';
END IF;
IF COUNTER = "011" THEN
clk_high_cnt <= '1';
ELSE
clk_high_cnt <= '0';
END IF;
END IF;
END PROCESS;
-- div_1 generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
div_1 <= '0';
ELSIF RISING_EDGE(clkin) THEN
IF clk_low_cnt = '1' THEN
div_1 <= NOT div_1;
END IF;
END IF;
END PROCESS;
-- clk_f generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
div_2 <= '0';
ELSIF FALLING_EDGE(clkin) THEN
IF clk_high_cnt = '1' THEN
div_2 <= NOT div_2;
END IF;
END IF;
END PROCESS;
clkout <= div_1 XOR div_2;
END arch;

50
CPLDs/GLUE_altera/clkdiv7.bsf

@ -0,0 +1,50 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 96)
(text "clkdiv7" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "reset_n" (rect 0 0 30 12)(font "Arial" ))
(text "reset_n" (rect 21 27 51 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "clkin" (rect 0 0 16 12)(font "Arial" ))
(text "clkin" (rect 21 43 37 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "clkout" (rect 0 0 22 12)(font "Arial" ))
(text "clkout" (rect 109 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 64)(line_width 1))
)
)

82
CPLDs/GLUE_altera/clkdiv7.vhd

@ -0,0 +1,82 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY clkdiv7 IS
PORT
(
reset_n : IN STD_LOGIC;
clkin : IN STD_LOGIC;
clkout : OUT STD_LOGIC
);
END clkdiv7;
ARCHITECTURE arch OF clkdiv7 IS
SIGNAL COUNTER : UNSIGNED(2 DOWNTO 0);
SIGNAL div_1 : STD_LOGIC;
SIGNAL div_2 : STD_LOGIC;
SIGNAL clk_low_cnt : STD_LOGIC;
SIGNAL clk_high_cnt : STD_LOGIC;
BEGIN
-- Counter generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
COUNTER <= "111";
ELSIF RISING_EDGE(clkin) THEN
IF COUNTER = "110" THEN
COUNTER <= "000";
ELSE
COUNTER <= COUNTER + 1;
END IF;
END IF;
END PROCESS;
-- clk_r generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
clk_low_cnt <= '0';
clk_high_cnt <= '0';
ELSIF RISING_EDGE(clkin) THEN
IF COUNTER = "000" THEN
clk_low_cnt <= '1';
ELSE
clk_low_cnt <= '0';
END IF;
IF COUNTER = "100" THEN
clk_high_cnt <= '1';
ELSE
clk_high_cnt <= '0';
END IF;
END IF;
END PROCESS;
-- div_1 generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
div_1 <= '0';
ELSIF RISING_EDGE(clkin) THEN
IF clk_low_cnt = '1' THEN
div_1 <= NOT div_1;
END IF;
END IF;
END PROCESS;
-- clk_f generation
PROCESS(clkin, reset_n)
BEGIN
IF (reset_n = '0') THEN
div_2 <= '0';
ELSIF FALLING_EDGE(clkin) THEN
IF clk_high_cnt = '1' THEN
div_2 <= NOT div_2;
END IF;
END IF;
END PROCESS;
clkout <= div_1 XOR div_2;
END arch;

218
CPLDs/GLUE_altera/t030glue.bsf

@ -0,0 +1,218 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 216 352)
(text "t030glue" (rect 5 0 36 12)(font "Arial" ))
(text "inst" (rect 8 320 20 332)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "reset_n" (rect 0 0 30 12)(font "Arial" ))
(text "reset_n" (rect 21 27 51 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "cpuclk" (rect 0 0 24 12)(font "Arial" ))
(text "cpuclk" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "as_n" (rect 0 0 20 12)(font "Arial" ))
(text "as_n" (rect 21 59 41 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "ds_n" (rect 0 0 20 12)(font "Arial" ))
(text "ds_n" (rect 21 75 41 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "rw" (rect 0 0 9 12)(font "Arial" ))
(text "rw" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "ah[26..19]" (rect 0 0 37 12)(font "Arial" ))
(text "ah[26..19]" (rect 21 107 58 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "al[3..0]" (rect 0 0 25 12)(font "Arial" ))
(text "al[3..0]" (rect 21 123 46 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "fc[2..0]" (rect 0 0 28 12)(font "Arial" ))
(text "fc[2..0]" (rect 21 139 49 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "mfp_dtack_n" (rect 0 0 54 12)(font "Arial" ))
(text "mfp_dtack_n" (rect 21 155 75 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 200 32)
(output)
(text "dsack[1..0]" (rect 0 0 42 12)(font "Arial" ))
(text "dsack[1..0]" (rect 137 27 179 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(port
(pt 200 48)
(output)
(text "berr_n" (rect 0 0 27 12)(font "Arial" ))
(text "berr_n" (rect 152 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 1))
)
(port
(pt 200 64)
(output)
(text "avec_n" (rect 0 0 30 12)(font "Arial" ))
(text "avec_n" (rect 149 59 179 71)(font "Arial" ))
(line (pt 200 64)(pt 184 64)(line_width 1))
)
(port
(pt 200 80)
(output)
(text "ciin_n" (rect 0 0 22 12)(font "Arial" ))
(text "ciin_n" (rect 157 75 179 87)(font "Arial" ))
(line (pt 200 80)(pt 184 80)(line_width 1))
)
(port
(pt 200 96)
(output)
(text "rw_inv" (rect 0 0 27 12)(font "Arial" ))
(text "rw_inv" (rect 152 91 179 103)(font "Arial" ))
(line (pt 200 96)(pt 184 96)(line_width 1))
)
(port
(pt 200 112)
(output)
(text "romce_n" (rect 0 0 36 12)(font "Arial" ))
(text "romce_n" (rect 143 107 179 119)(font "Arial" ))
(line (pt 200 112)(pt 184 112)(line_width 1))
)
(port
(pt 200 128)
(output)
(text "ramce_n" (rect 0 0 36 12)(font "Arial" ))
(text "ramce_n" (rect 143 123 179 135)(font "Arial" ))
(line (pt 200 128)(pt 184 128)(line_width 1))
)
(port
(pt 200 144)
(output)
(text "mfpcs_n" (rect 0 0 36 12)(font "Arial" ))
(text "mfpcs_n" (rect 143 139 179 151)(font "Arial" ))
(line (pt 200 144)(pt 184 144)(line_width 1))
)
(port
(pt 200 160)
(output)
(text "spics_n" (rect 0 0 30 12)(font "Arial" ))
(text "spics_n" (rect 149 155 179 167)(font "Arial" ))
(line (pt 200 160)(pt 184 160)(line_width 1))
)
(port
(pt 200 176)
(output)
(text "dramcs_n" (rect 0 0 41 12)(font "Arial" ))
(text "dramcs_n" (rect 138 171 179 183)(font "Arial" ))
(line (pt 200 176)(pt 184 176)(line_width 1))
)
(port
(pt 200 192)
(output)
(text "ide_cs0_n" (rect 0 0 41 12)(font "Arial" ))
(text "ide_cs0_n" (rect 138 187 179 199)(font "Arial" ))
(line (pt 200 192)(pt 184 192)(line_width 1))
)
(port
(pt 200 208)
(output)
(text "ide_cs1_n" (rect 0 0 40 12)(font "Arial" ))
(text "ide_cs1_n" (rect 139 203 179 215)(font "Arial" ))
(line (pt 200 208)(pt 184 208)(line_width 1))
)
(port
(pt 200 224)
(output)
(text "ide_rd_n" (rect 0 0 35 12)(font "Arial" ))
(text "ide_rd_n" (rect 144 219 179 231)(font "Arial" ))
(line (pt 200 224)(pt 184 224)(line_width 1))
)
(port
(pt 200 240)
(output)
(text "ide_wr_n" (rect 0 0 36 12)(font "Arial" ))
(text "ide_wr_n" (rect 143 235 179 247)(font "Arial" ))
(line (pt 200 240)(pt 184 240)(line_width 1))
)
(port
(pt 200 256)
(output)
(text "ide_a[2..0]" (rect 0 0 41 12)(font "Arial" ))
(text "ide_a[2..0]" (rect 138 251 179 263)(font "Arial" ))
(line (pt 200 256)(pt 184 256)(line_width 3))
)
(port
(pt 200 272)
(output)
(text "bufce_n" (rect 0 0 33 12)(font "Arial" ))
(text "bufce_n" (rect 146 267 179 279)(font "Arial" ))
(line (pt 200 272)(pt 184 272)(line_width 1))
)
(port
(pt 200 288)
(output)
(text "spids" (rect 0 0 20 12)(font "Arial" ))
(text "spids" (rect 159 283 179 295)(font "Arial" ))
(line (pt 200 288)(pt 184 288)(line_width 1))
)
(port
(pt 200 304)
(output)
(text "mfpiack_n" (rect 0 0 42 12)(font "Arial" ))
(text "mfpiack_n" (rect 137 299 179 311)(font "Arial" ))
(line (pt 200 304)(pt 184 304)(line_width 1))
)
(drawing
(rectangle (rect 16 16 184 320)(line_width 1))
)
)

111
CPLDs/GLUE_altera/t030glue.vhd

@ -0,0 +1,111 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY t030glue IS
PORT
(
reset_n : IN std_logic;
cpuclk : IN std_logic;
as_n : IN std_logic;
ds_n : IN std_logic;
rw : IN std_logic;
ah : IN std_logic_vector (26 downto 19);
al : IN std_logic_vector (3 downto 0);
fc : IN std_logic_vector (2 downto 0);
mfp_dtack_n : IN std_logic;
dsack : OUT std_logic_vector (1 downto 0);
berr_n : OUT std_logic;
avec_n : OUT std_logic;
ciin_n : OUT std_logic;
rw_inv : OUT std_logic;
romce_n : BUFFER std_logic;
ramce_n : BUFFER std_logic;
mfpcs_n : BUFFER std_logic;
spics_n : BUFFER std_logic;
dramcs_n : OUT std_logic;
ide_cs0_n : OUT std_logic;
ide_cs1_n : OUT std_logic;
ide_rd_n : OUT std_logic;
ide_wr_n : OUT std_logic;
ide_a : OUT std_logic_vector (2 downto 0);
bufce_n : OUT std_logic;
spids : OUT std_logic;
mfpiack_n : OUT std_logic
);
END ENTITY t030glue;
ARCHITECTURE arch OF t030glue IS
SIGNAL dtack_s : std_logic_vector (2 downto 0);